1. Technical Field
The embodiments herein generally relate to integrated circuits (IC's), and, more particularly, to optimizing chip pad area in integrated circuits.
2. Description of the Related Art
Chip pads are normally optimized in shape to fit as many pads as possible in a chip pad ring (area around the silicon core). Typically, the dimensions of the chip pads, particularly, the length (L) is kept as long as possible. This is done to facilitate access by external means during the course of IC fabrication. As an example, a chip pad is designed with a larger length that is sufficient to facilitate an IC packaging process where metal wires are bonded to the chip pads via mechanical means.
FIG. 1 illustrates a traditional pin count pad 100. The pin count pad 100 includes dimensions L and W. L is the length of the pad and W is the width of the pad. The pad 100 includes stack of circuits 102, and long electrostatic discharge (ESD) cells 104. Since, the chip pad includes long ESD cells 104, the length of the pad 100 is relatively large as shown in FIG. 1.
FIG. 2 illustrates a traditional integrated circuit chip (IC) having the pin count pads 100, the stack of circuits 102, and the long ESD cells 104 of FIG. 1, as well as a chip core 202, and a wasted area 204 (i.e., an area unoccupied by circuitry or I/O elements). The pin count pads 100 are mounted along the chip core 202. However, for chips with few numbers of pins, it results in wasting large portion of area (e.g., the wasted area 204) of the silicon area as pads are sparse in a chip pad ring. Accordingly, there remains a need for a re-layout that will optimize the silicon chip area.